#ifndef __GILBRALTAR_BCM__
#define __GILBRALTAR_BCM__

#define ARM_IO_BASE 0x107c000000UL

// System timers
#define ARM_SYSTIMER_BASE (ARM_IO_BASE + 0x3000)
#define ARM_SYSTIMER_CS (ARM_SYSTIMER_BASE + 0x00)
#define ARM_SYSTIMER_CLO (ARM_SYSTIMER_BASE + 0x04)
#define ARM_SYSTIMER_CHI (ARM_SYSTIMER_BASE + 0x08)

// Interrupt Controller
#define ARM_IC_BASE (ARM_IO_BASE + 0xb000)

#define ARM_IC_FIQ_CONTROL (ARM_IO_BASE + 0x20c)

// General Purpose I/O #2
#define ARM_GPIO2_BASE (ARM_IO_BASE + 0x1517c00)

#define ARM_GPIO2_DATA0 (ARM_GPIO2_BASE + 0x04)
#define ARM_GPIO2_IODIR0 (ARM_GPIO2_BASE + 0x08)

// Power Manager
#define ARM_PM_BASE (ARM_IO_BASE + 0x1200000)

#define ARM_PM_RSTC (ARM_PM_BASE + 0x1c)
#define ARM_PM_RSTS (ARM_PM_BASE + 0x20)
#define ARM_PM_WDOG (ARM_PM_BASE + 0x24)
#define ARM_PM_PADS0 (ARM_PM_BASE + 0x2c)
#define ARM_PM_PADS1 (ARM_PM_BASE + 0x30)
#define ARM_PM_PADS2 (ARM_PM_BASE + 0x34)

#define ARM_PM_PASSWD (0x5a << 24)

#endif