#ifndef __GILBRALTAR_TRANSITION_TABLE__
#define __GILBRALTAR_TRANSITION_TABLE__

#include <stddef.h>
#include <stdint.h>

#define ARMV8MMU_TABLE_ENTRIES 8192

// index into MAIR_EL1 register
#define ATTR_INDX_NORMAL 0
#define ATTR_INDX_DEVICE 1
#define ATTR_INDX_COHERENT 2

// Level 2
struct __attribute__((packed)) TARMV8MMU_LEVEL2_TABLE_DESCRIPTOR {
  uint64_t value11 : 2, // set to 3
      ignored1 : 14,    // set to 0
      table_addr : 32,  // table base [47:16]
      reserved0 : 4,    // set to 0
      ignored2 : 7,     // set to 0
      pxn_table : 1,    // set to 0
      uxn_table : 1,    // set to 0
      ap_table : 2,
#define AP_TABLE_ALL_ACCESS 0
      ns_table : 1 // RES0, set to 0
      ;
};

#define ARMV8MMUL2TABLEADDR(addr) (((addr) >> 16) & 0xffffffff)
#define ARMV8MMUL2TABLEPTR(table) ((void *)((table) << 16))

struct __attribute__((packed)) TARMV8MMU_LEVEL2_BLOCK_DESCRIPTOR {
  uint64_t value01 : 2, // set to 1
                        // lower attributes : 10,
      attr_indx : 3,    // [2:0], see MAIR_EL1
      ns : 1,           // RES0, set to 0
      ap : 2,           // [2:1]
#define ATTR_IB_AP_RW_EL1 0
#define ATTR_IB_AP_RW_ALL 1
#define ATTR_IB_AP_RO_EL1 2
#define ATTR_IB_AP_RO_ALL 3
      sh : 2, // [1:0]
#define ATTR_IB_SH_NON_SHAREABLE 0
#define ATTR_IB_SH_OUTER_SHAREABLE 2
#define ATTR_IB_SH_INNER_SHAREABLE 3
      af : 1,           // set to 1, will fault otherwise
      ng : 1,           // set to 0
      reserved0_1 : 17, // set to 0
      output_addr : 19, // [47:29]
      reserved0_2 : 4,  // set to 0
      // upper attributes : 12
      continuous : 1, // set to 0
      pxn : 1,        // set to 0, 1 for device memory
      uxn : 1,        // set to 1
      ignored : 9     // set to 0
      ;
};

#define ARMV8MMU_LEVEL2_BLOCK_SIZE (512 * MEGABYTE)
#define ARMV8MMUL2BLOCKADDR(addr) (((addr) >> 29) & 0x7ffff)
#define ARMV8MMUL2BLOCKPTR(block) ((void *)((table) << 29))

struct __attribute__((packed)) TARMV8MMU_LEVEL2_INVALID_DESCRIPTOR {
  uint64_t value0 : 1, // set to 0
      ignored : 63;
};

union __attribute__((packed)) TARMV8MMU_LEVEL2_DESCRIPTOR {
  struct TARMV8MMU_LEVEL2_TABLE_DESCRIPTOR table;
  struct TARMV8MMU_LEVEL2_BLOCK_DESCRIPTOR block;
  struct TARMV8MMU_LEVEL2_INVALID_DESCRIPTOR invalid;
};

// Level  3
struct __attribute__((packed)) TARMV8MMU_LEVEL3_PAGE_DESCRIPTOR {
  uint64_t value11 : 2, // set to 3
                        // lower attributes : 10,
      attr_indx : 3,    // [2:0], see MAIR_EL1
      ns : 1,           // RES0, set to 0
      ap : 2,           // [2:1]
      sh : 2,           // [1:0]
      af : 1,           // set to 1, will fault otherwise
      ng : 1,           // set to 0
      reserved0_1 : 4,  // set to 0
      output_addr : 32, // [47:16]
      reserved0_2 : 4,  // set to 0
      // upper attributes : 12
      continuous : 1, // set to 0
      pxn : 1,        // set to 0, 1 for device memory
      uxn : 1,        // set to 1
      ignored : 9     // set to 0
      ;
};

#define ARMV8MMU_LEVEL3_PAGE_SIZE 0x10000
#define ARMV8MMUL3PAGEADDR(addr) (((addr) >> 16) & 0xffffffff)
#define ARMV8MMUL3PAGEPTR(page) ((void *)((page) << 16))

struct __attribute__((packed)) TARMV8MMU_LEVEL3_INVALID_DESCRIPTOR {
  uint64_t value0 : 1, // set to 0
      ignored : 63;
};

union __attribute__((packed)) TARMV8MMU_LEVEL3_DESCRIPTOR {
  struct TARMV8MMU_LEVEL3_PAGE_DESCRIPTOR page;
  struct TARMV8MMU_LEVEL3_INVALID_DESCRIPTOR invalid;
};

void gilbraltar_translation_table_init(size_t);
uintptr_t gilbraltar_translation_table_base(void);

#endif