port argument
This commit is contained in:
parent
de7c0ca8a7
commit
f10e6257be
2 changed files with 3 additions and 3 deletions
|
@ -49,13 +49,13 @@ module Make (T : Mirage_time.S) (S : Mirage_stack.V4) = struct
|
||||||
in
|
in
|
||||||
one ()
|
one ()
|
||||||
|
|
||||||
let create ?(interval = 10) ?hostname stack dst =
|
let create ?(interval = 10) ?hostname dst ?(port = 8094) stack =
|
||||||
let get_cache, reporter = Metrics.cache_reporter () in
|
let get_cache, reporter = Metrics.cache_reporter () in
|
||||||
Metrics.set_reporter reporter;
|
Metrics.set_reporter reporter;
|
||||||
Metrics.enable_all ();
|
Metrics.enable_all ();
|
||||||
Metrics_lwt.init_periodic (fun () -> T.sleep_ns (Duration.of_sec interval));
|
Metrics_lwt.init_periodic (fun () -> T.sleep_ns (Duration.of_sec interval));
|
||||||
Metrics_lwt.periodically (OS.MM.malloc_metrics ~tags:Metrics.Tags.[]);
|
Metrics_lwt.periodically (OS.MM.malloc_metrics ~tags:Metrics.Tags.[]);
|
||||||
let host = match hostname with None -> [] | Some host -> [vmname host] in
|
let host = match hostname with None -> [] | Some host -> [vmname host] in
|
||||||
Lwt.async (timer_loop get_cache host interval stack dst)
|
Lwt.async (timer_loop get_cache host interval stack (dst, port))
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
@ -2,5 +2,5 @@ val vmname : string -> Metrics.field
|
||||||
(** [vmname name] creates a [tag] with the virtual machine name. *)
|
(** [vmname name] creates a [tag] with the virtual machine name. *)
|
||||||
|
|
||||||
module Make (T : Mirage_time.S) (S : Mirage_stack.V4) : sig
|
module Make (T : Mirage_time.S) (S : Mirage_stack.V4) : sig
|
||||||
val create : ?interval:int -> ?hostname:string -> S.t -> Ipaddr.V4.t * int -> unit
|
val create : ?interval:int -> ?hostname:string -> Ipaddr.V4.t -> ?port:int -> S.t -> unit
|
||||||
end
|
end
|
||||||
|
|
Loading…
Reference in a new issue