43 lines
2 KiB
OCaml
43 lines
2 KiB
OCaml
(** The Lwt variation of Cachet implies a point of cooperation ([Lwt.pause]) as
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soon as the syscall [map] is called. In other words, a task developed with
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Cachet_lwt will make itself available to be rescheduled if we internally
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call [map] instead of using the cache.
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In the event that the functions below were to use the cache, they would
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retain the exclusive right to execute and would not allow any cooperation
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points to appear.
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Such an approach increases the task's availability if it does I/O in
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cooperation with other tasks that would also like to do I/O. *)
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val load : 'fd Cachet.t -> ?len:int -> int -> Cachet.slice option Lwt.t
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val get_int8 : 'fd Cachet.t -> int -> int Lwt.t
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(** [get_int8 t logical_address] is [t]'s signed 8-bit integer starting at byte
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index [logical_address].
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@raise Out_of_bounds if [logical_address] is not accessible. *)
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val get_uint8 : 'fd Cachet.t -> int -> int Lwt.t
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(** [get_uint8 t logical_address] is [t]'s unsigned 8-bit integer starting at
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byte index [logical_address].
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@raise Out_of_bounds if [logical_address] is not accessible. *)
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val get_uint16_ne : 'fd Cachet.t -> int -> int Lwt.t
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val get_uint16_le : 'fd Cachet.t -> int -> int Lwt.t
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val get_uint16_be : 'fd Cachet.t -> int -> int Lwt.t
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val get_int16_ne : 'fd Cachet.t -> int -> int Lwt.t
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val get_int16_le : 'fd Cachet.t -> int -> int Lwt.t
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val get_int16_be : 'fd Cachet.t -> int -> int Lwt.t
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val get_int32_ne : 'fd Cachet.t -> int -> int32 Lwt.t
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val get_int32_le : 'fd Cachet.t -> int -> int32 Lwt.t
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val get_int32_be : 'fd Cachet.t -> int -> int32 Lwt.t
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val get_int64_ne : 'fd Cachet.t -> int -> int64 Lwt.t
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val get_int64_le : 'fd Cachet.t -> int -> int64 Lwt.t
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val get_int64_be : 'fd Cachet.t -> int -> int64 Lwt.t
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val get_string : 'fd Cachet.t -> len:int -> int -> string Lwt.t
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val next : 'fd Cachet.t -> Cachet.slice -> Cachet.slice option Lwt.t
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val blit_to_bytes :
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'fd Cachet.t -> src_off:int -> bytes -> dst_off:int -> len:int -> unit Lwt.t
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